1. Field
One or more example embodiments of the present disclosure relate to a memory access address translating apparatus and method, and more particularly, to a memory access address translating apparatus and method using a bank interleaving scheme.
2. Description of the Related Art
A memory, such as a dynamic random access memory (DRAM), an asynchronous DRAM (SDRAM), and the like, may include a plurality of banks. A memory system may allocate a memory address to each of the plurality of banks.
Referring to FIG. 1A, the memory system may allocate the memory address in an order 10 of a bank, a row, and a column. In this example, the most significant two bits 110 may be used as a bank address that distinguishes the plurality of banks, twelve upper bits 120 may be used as a row address that distinguishes a plurality of rows, and remaining nine lower bits 130 may be used as a column address that distinguishes a plurality of columns. A single memory may include a plurality of banks, a bank may include a plurality of rows, and a row may include a plurality of columns. In this example, a DRAM having a 16-bit output may have a bank of 4 Mbytes.
Referring to FIG. 1B, the memory system may allocate a memory address in an order 20 of a row, a bank, and a column. In this example, a single memory may include a plurality of rows, a row may include a plurality of banks, and a bank may include a plurality of columns. In this example, a DRAM having a 16-bit output may have a bank of 1 Kilobyte.
In general, the memory system may store, in a memory, input images based on a macro block unit. Here, data stored in each successive macro block is usually stored in the same bank.
To read the data stored in the bank, preparation time to prepare the reading may be required. Accordingly, when a plurality of data stored, in the same bank is read, overhead may increase due to the preparation time expended for each piece of data.
Thus, there is a desire for a memory access technology that may reduce or remove the preparation time expended for accessing a memory and that may decrease overhead.